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TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Features
! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Single chip solution with only a few external components Stand-alone fixed-frequency transceiver operation modes Programmable multi-channel transceiver operation modes Low current consumption in active mode and very low standby current PLL-stabilized RF VCO (LO) with external varactor diode Lock detection in programmable channel applications 3wire bus serial control interface FSK/ASK modulation selection FSK for digital data and FM for analog signal reception RSSI allows signal strength indication and ASK detection Switchable LNA gain for improved dynamic range Automatic PA turn-on after PLL lock FM possible with external varactor ASK modulation achieved by on/off keying AFC option for extended input frequency acceptance range Surface mount package LQFP32
Ordering Information
TH7121 (TH7120-02)
Part No. (Engineering Samples)
Application Examples
! ! ! ! ! !
General bi-directional half duplex digital data transmission or analog signal transmission Low-power telemetry Alarm and security systems Keyless car and central locking Domotics Model control
P
IN IM L E R
Temperature Code E (-40 C to 85 C)
Y R A
Package Code NE (LQFP32)
Technical Data Overview
! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Frequency range: 300 MHz to 930 MHz for programmable channel applications 315 MHz, 433 MHz, 868 MHz or 915 MHz fixed-frequency single-channel variants Power supply range: 2.5 V to 5.5 V Temperature range: -40 C to +85 C Standby current: 50 nA Operating current: 6.0 mA in receive mode at low gain Operating current 9.0 mA in transmit mode at 0 dBm output power Adjustable output power range from -15 dBm to +6 dBm Sensitivity: -103 dBm at FSK with 150 kHz IF filter BW Sensitivity: -105 dBm at ASK with 150 kHz IF filter BW Maximum data rate for FSK and ASK: 60 kbit/s NRZ Maximum input level: -10 dBm at FSK and -20 dBm at ASK Input frequency acceptance: 50 kHz (with AFC option) Frequency deviation range: 5 kHz to 100 kHz Maximum analog modulation frequency: 20 kHz 3 MHz to 12 MHz crystal reference
3901007121 Rev. 001
Page 1 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
General Description
The TH7120 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multi-channel programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used for ISM, SRD or any other application operating in the frequency ranging of 300 MHz to 930 MHz. The TH7120 transceiver IC consists of the following building blocks: " " " " " " " " " " " " " " Low-noise amplifier (LNA) for high-sensitivity RF signal reception with switchable gain Mixer (MIX) for RF-to-IF down-conversion IF amplifier (IFA) to amplify and limit the IF signal and for RSSI generation Phase-coincidence demodulator with external ceramic discriminator (FSK Demodulator) Operational amplifier, connected to demodulator output (OA1) Operational amplifier, integrator circuit at FSK-AFC mode (OA2) Control logic with 3wire bus serial control interface (SCI) Reference oscillator (RO) with external crystal Reference divider (R counter) Programmable divider (N/A counter) Phase-frequency detector (PFD) Charge pump (CP) Voltage control oscillator (VCO) with internal varactor Power amplifier (PA) with adjustable output power
The transceiver can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixedfrequency device. After power up, the transceiver is set to fixed-frequency mode. In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC in order to set the desired frequency of operation. The logic levels at pins FS0/SDEN and FS1/LD must not be changed after power up in order to remain in fixed-frequency mode. Channel frequency FS0/SDEN FS1/LD
P
L E R
1 0 0 0
IN IM
868.3 MHz 0 0
Y R A
915.0 MHz 0 1 1 1
433.92 MHz
315.0 MHz
After the first logic level change at pin FS0/SDEN, the transceiver enters into programmable mode while pin FS1/LD is now a PLL lock detector output. In this mode, the user can set any PLL frequency or mode of operation by the SCI. In the fixed-frequency mode, the user can set the transceiver to Standby, Receive, Transmit or Idle (only PLL synthesizer active) mode via control pins RE/SCLK and TE/SDTA. Operation mode RE/SCLK TE/SDTA Standby Receive 1 0 Transmit 0 1 Idle 1 1
3901007121 Rev. 001
Page 2 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Block Diagram
5 4
OUT_DTA
INT2
INT1
8
SCI
OA2
OA1
SDTA SDEN
VEE_DIG
18
6 OUT_DEM
bias
200k
FS0/SDEN
Control Logic
TE/SDTA RE/SCLK ASK/FSK IN_DTA VEE_RO FSK
12 13 15 16
FSK Demodulator
17
14
SCLK
VCC_DIG
FS1/LD FSK_SW
19
OUT_MIX1
32
IN_MIX OUT_LNA
28 30
IN_LNA
26
OUT_PA
VEE_LNA
27
LNA
29
Figure 1:
TH7121 block diagram
3901007121 Rev. 001
Page 3 of 28
25
PA
GAIN_LNA
24 PS_PA
ASK
23 TNK_LO 20 VCC_PLL
MIX
VCO
P
LO
N counter
L E R
VCC_IF
2
IN_IFA
1
VEE_IF
31
IF
21 LF
IN IM
RO
22 VEE_PLL 10 RO
Y R A
3 IN_DEM
MIX
1.5pF
R counter
7 RSSI
IFA
RO
11
9
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Pin Definition and Description
Pin No. 1 Name IN_IFA I/O Type input
2.2k
Functional Schematic
VCC 3.1k 3.1k
Description IF amplifier input, approx. 2 k single-ended
IN_IFA 1
140A VEE
2
VCC_IF
supply
3
IN_DEM
analog I/O
77k
VCC
IN_DEM 3
4
INT2
output
8
OUT_DTA output
5
INT1
P
L E R
input
VCC 120
INT2 4
8 OUT_DTA
IN IM
1.5p 10A 100A VEE VCC VEE VCC
bias
Y R A
integrator output OA2 output OA1 inverting inputs OA1 and OA2 demodulator output and noninverting input OA1
positive supply of LNA, MIX, IFA, FSK Demodulator, PA, OA1 and OA2 IF amplifier output and demodulator input, connection to external ceramic discriminator
INT1 5
OA2
OUT_DEM 6
120
6
OUT_DEM analog I/O
120
VCC
VEE 200k
VEE
520k
+
10.5p VEE
7
RSSI
output
520k
OA1
VCC
VCC 5A
10.5p
1k
RSSI output
RSSI 7
120
5A VEE VEE
3901007121 Rev. 001
Page 4 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Pin No. 9 10
Name VEE_RO RO
I/O Type ground analog I/O
Functional Schematic
Description ground of RO
VCC 2.6A
RO input, base of bipolar transistor
40p
RO 10
40p
39k VEE VCC
11
FSK_SW
analog I/O
FSK_SW 11
VEE
12
IN_DTA
input
IN_DTA 12 RE/SCLK 15 16 TE/SDTA
15
RE/SCLK
input
16
TE/SDTA
13
ASK/FSK
17
FS0/SDEN input
P
L E R
input input supply ground input
FS1/LD 19
IN IM
VCC 120 120k VEE VCC 120 VEE VCC
Y R A
ASK/FSK modulation data input, pull down resistor 120k receiver enable input / clock input for the shift register, pull down resistor 120k transmitter enable input / serial data input, pull down resistor 120k ASK/FSK mode select input frequency select input / serial data enable input positive supply of serial port and control logic ground of serial port and control logic frequency select input / lock detector output
FSK pulling pin, switch to ground or OPEN
ASK/FSK 13
17 FS0/SDEN
14 18 19
VCC_DIG VEE_DIG FS1/LD
120
VEE
20 22
VCC_PLL VEE_PLL
supply ground
positive supply of PLL frequency synthesizer ground of PLL frequency synthesizer
3901007121 Rev. 001
Page 5 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Pin No. 21
Name LF
I/O Type analog I/O
Functional Schematic
VCC
Description charge pump output, connection to external loop filter
LF 21
120
23
TNK_LO
analog I/O
VCC
TNK_LO 23
VEE 33 33
VCO open-collector output, connection to external LC tank
VEE
24
PS_PA
analog I/O
VCC
VCC
PS_PA 24
120
25
OUT_PA
27 28
VEE_LNA
P
L E R
output
25
VEE
VEE
IN IM
VEE VCC VEE
Y R A
power-setting input power amplifier opencollector output ground of LNA and PA LNA open-collector output, connection to external LC tank at RF
OUT_PA
ground output
bias
OUT_LNA
OUT_LNA 28
37 3.8k
VEE 40p
26
IN_LNA
input
IN_LNA 26
VEE
LNA input, approx. 50 single-ended
29
GAIN_LNA input
VCC
LNA gain control input
GAIN_LNA 29
120
VEE
3901007121 Rev. 001
Page 6 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Pin No. 30
Name IN_MIX
I/O Type input
IN_MIX 30
Functional Schematic
VCC 210
Description mixer input, approx. 200 single-ended
LO
bias
VEE
VEE
31 32
VEE_IF OUT_MIX
ground output
OUT_MIX 32
VCC
100
P
L E R
IN IM
VEE
Y R A
ground of IFA, Demodulator, OA1 and OA2 mixer output, approx. 330 single-ended
3901007121 Rev. 001
Page 7 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Stand-Alone Fixed-Frequency Operation
After power up the transceiver is set to fixed-frequency mode. In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC to set the desired frequency of operation. The logic levels at pins FS0/SDEN and FS1/LD must not be changed after power up in order to remain in fixed-frequency mode. The default settings of the control word bits in stand-alone mode are described in the frequency selection table.
Frequency Selection Channel frequency FS0/SDEN FS1/LD Reference oscillator frequency R counter ratio in RX mode PFD frequency in RX mode N/A counter ratio in RX mode VCO frequency in RX mode RX frequency R counter ratio in TX mode PFD frequency in TX mode N/A counter ratio in TX mode VCO frequency in TX mode TX frequency IF frequency in RX mode 16 446.91 kHz 947 423.22 MHz 433.92 MHz 16 16 446.91 kHz 1919 857.60 MHz 868.30 MHz 16 446.91 kHz 1943 433.92 MHz 1 0 868.3 MHz 0 0 7.1505 MHz 315 MHz 1 1 18 915 MHz 0 1 30
397.25 kHz 766
P
L E R
446.91 kHz 971
433.92 MHz 433.92 MHz 10.7 MHz
IN IM
868.30 MHz 868.30 MHz 10.7 MHz
304.30 MHz 315.00 MHz 18 397.25 kHz 793
Y R A
238.35 kHz 3794 904.30 MHz 915.00 MHz 30 238.35 kHz 3839 915.00 MHz 915.00 MHz 10.7 MHz
315.00 MHz 315.00 MHz 10.7 MHz
3901007121 Rev. 001
Page 8 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Default Register Settings After Power-up Channel Channel Channel Channel `00' `01' `10' `11' 868.3 433.92 915.0 315.0 MHz MHz MHz MHz
0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0
Bits
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A-word symbols
not used DI_MODE MODUL HighCur LOCK_MODE PA_AUTO Pow1 Pow0 MIXG LNAG TE RE RR9 RR8 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0
B-word symbols
not used not used EnDelPLL LNAHYST EnAdj EnFM Max2 Max1 Max0 Min2 Min1 Min0 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0
Channel Channel Channel Channel `00' `01' `10' `11' 868.3 433.92 915.0 315.0 MHz MHz MHz MHz
0 0 1 1 0 0 1 1 1 0 1 1
Bits
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C-word symbols
LNAGI_E POLAR High2 High1 UP NR16 NR15 NR14 NR13 NR12 NR11 NR10 NR9 NR8 NR7 NR6 NR5 NR4 NR3 NR2 NR1 NR0
P
L E R
0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0
Channel Channel Channel Channel `00' `01' `10' `11' 868.3 433.92 915.0 315.0 MHz MHz MHz MHz
IN IM
B-word symbols
MODUL_CTR LD_TM1 LD_TM0 ER_TM1 ER_TM0 NT16 NT15 NT14 NT13 NT12 NT11 NT10 NT9 NT8 NT7 NT6 NT5 NT4 NT3 NT2 NT1 NT0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1
0 0 0 0 0 1 0 0 0 0
Y R A
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0
Channel Channel Channel Channel `00' `01' `10' `11' 868.3 433.92 915.0 315.0 MHz MHz MHz MHz 0
1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1
3901007121 Rev. 001
Page 9 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Programmable Channel Operation
Serial Control Interface Description A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in multichannel mode (see Fig. 2). At each rising edge of the SCLK signal, the logic value on the SDTA pin is written into a 24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches on the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first two bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 2 and 3. Table REGISTER SETTINGS describes the function of each bit.
SDTA SCLK
24-BIT SHIFT REGISTER
2
22
22
A - LATCH
SDEN
Figure 2: SCI block diagram
Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as well as in standby mode.
P
tCS
L E R
ADDR DECODER
bit 22 tCH
`00' `01'
`10' `11'
IN IM
22 22
LSB bit 1 bit 0
22
B - LATCH
Y R A
22 A-word 22 B-word 22 C-word 22 D-word
Invalid data
C - LATCH
D - LATCH
Invalid data SDTA
MSB bit 23
SCLK tCWL tCWH
SDEN tES
Figure 3: Serial data input timing
tEW
tEH
3901007121 Rev. 001
Page 10 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
SCI Words A-word
MSB 23 22 LSB 21 X not used 20 X DI_MODE 19 X MODUL 18 X HighCur 17 X LOCK_MODE 16 X PA_AUTO 15 X Pow1 14 X Pow0 13 X MIXG 12 X LNAG 11 X TE 10 X RE 9 X RR9 8 X RR8 7 X RR7 6 X RR6 5 X RR5 4 X RR4 3 X RR3 2 X RR2 1 X RR1 1 X RT1 1 X NR1 1 X NT1 0 X RR0 LSB 0 X LSB 12 X NR12 11 X NR11 10 X NR10 9 X NR9 8 X NR8 7 X NR7 6 X NR6 5 X NR5 4 X NR4 3 X NR3 2 X NR2 0 X NR0 LSB 22 21 X MODUL_CTR 20 X LD_TM1 19 X LD_TM0 18 X ER_TM1 17 X ER_TM0 16 X NT16 15 X NT15 14 X NT14 13 X NT13 12 X NT12 11 X NT11 10 X NT10 9 X NT9 8 X NT8 7 X NT7 6 X NT6 5 X NT5 4 X NT4 3 X NT3 2 X NT2 0 X NT0 RT0
0 0 ADDR
B-word
MSB 23 22 21 X not used 20 X not used 19 X EnDelPLL 18 X LNAHYST 17 X EnAdj 16 X EnFm 15 X Max2 14 X Max1 13 X Max0 12 X Min2 11 X Min1 10 X Min0 9 X RT9 8 X RT8 7 X RT7
RT6
RT5
RT4
RT3
C-word
MSB 23 22 21 X
POLAR
High2
High1
NR16
NR15
NR14
LNAGI_E
D-word
MSB 23
1 1 ADDR
3901007121 Rev. 001
NR13
UP
1 0 ADDR
P
20 X
19 X
L E R
18 X 17 X 16 X 15 X 14 X 13 X
Page 11 of 28
RT2
0 1 ADDR
6 X
IN IM
Y R A
5 X 4 X 3 X 2 X
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Register Settings A-word Symbol Software button RR9:RR0 RR9:RR0 TE:RE [11:10] 2 `00' `11' OPMODE `10' `01' LNAG LNAGAIN MIXG MIXGAIN Pow1:Pow0 [15:14] 2 [13] 1 [12] 1 `0' `1' `0' `1' [9:0] 10 Reference divider ratio in RX mode Select active mode at programmable-channel application: Standby mode Idle mode Transmit mode Receive mode low LNA gain high LNA gain Select LNA gain at internal gain control: Bits No. Description
Select mixer conversion gain at programmable-channel application: low gain high gain
TXPOWER
PA_AUTO
PA_AUTO
P
L E R
`00' `01' `10' `11' `0' `1' [16] 1 [17] 1 `0' `1' [18] 1 `0' `1' [19] 1 `0' `1' [20] 1 `0'
Select output power at programmable-channel application: Pmax - 20 dBm Pmax - 12 dBm Pmax - 6 dBm Pmax Disable automatic PA turn-on after PLL lock: enabled disabled Select PFD output analyse mode of lock detecting: before lock only before and after lock. Select Charge Pump output current: 260 A 1300 A ASK FSK Select mode for input data: normal inverse
IN IM
Y R A
LOCK_MODE LOCK_MODE HighCur CPCUR MODUL ASK/FSK DI_MODE DI_MODE
Select modulation mode at internal modulation control:
`0' for space at ASK or fmin at FSK, `1' for mark at ASK or fmax at FSK `1' `1' for space at ASK or fmin at FSK, `0' for mark at ASK or fmax at FSK
not used
[21]
1
`X'
3901007121 Rev. 001
Page 12 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
B-word Symbol Software button RT9:RT0 RT9:RT0 Min2:Min0 [12:10] 3 `000' `001' `010' ROMIN `011' `100' `101' `110' `111' Max2:Max0 [15:13] 3 `000' `001' `010' `011' `100' `101' `110' `111' [9:0] 10 Reference divider ratio in TX mode Select minimum value of RO active current: 0 A 50 A 100 A 150 A 200 A 250 A 300 A Bits No. Description
ROMAX
EnFm
P
L E R
[16] [17] [18] 1 1 1 `1' `0' [19] 1 `1' `0' [20] [21] 1 1 `X' `X'
IN IM
350 A 0 A (RO is off) 50 A 100 A 150 A 200 A 250 A 300 A 350 A disabled enabled disabled enabled.
Select maximum value of RO active current:
Y R A
Test bit. Forced '0' for correct functioning. Test bit. Forced '0' for correct functioning. Enable LNA hysteresis:
EnAdj LNAHYST LNAHYST EnDelPLL EnDelPLL not used not used
Enable delayed start of the PLL:
3901007121 Rev. 001
Page 13 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
C-word Symbol Software button NR16:NR0 NR16:NR0 UP BAND High2:High1 [19:18] 2 `00' `01' VCOCUR `10' `11' POLAR [20] 1 `1' [17] 1 `1' `0' [16:0] 17 Feedback divider ratio in RX mode Select frequency band: up to 500 MHz 500 to 1000MHz Select VCO active current: low current (250 A) high1 current (450 A) high2 current (550 A) positive (1) standard current (350 A) Bits No. Description
PFDPOL
LNAGI_E LNACTRL
P
IN IM L E R
`0' negative (2) [21] 1 `0' `1'
Select Phase Detector polarity:
VCO OUTPUT FREQUENCY
Y R A
(1) (2) VCO INPUT VOLTAGE
Select LNA gain control mode:
external LNA gain control internal LNA gain control
3901007121 Rev. 001
Page 14 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
D-word Symbol Software button NT16:NT0 NT16:NT0 ER_TM1:ER_TM0 [18:17] 2 [16:0] 17 Feedback divider ratio in TX mode Select maximum enabled PFD output error for lock detecting (in reference frequency clocks): `00' ER_TM1:ER_TM0 `01' `10' `11' LD_TM1:LD_TM0 [20:19] 2 2 clocks 4 clocks 8 clocks 16 clocks Bits No. Description
Select minimum number of PFD reference frequency clocks before lock detecting: `00' 4 clocks `01' `10' `11'
LD_TM1:LD_TM0
MODUL_CTR MODCTRL
P
L E R
`0' `1'
[21]
1
Select mode of modulation control:
IN IM
16 clocks 64 clocks 256 clocks
Y R A
external modulation control internal modulation control
3901007121 Rev. 001
Page 15 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Technical Data
Absolute Maximum Ratings Parameter Supply voltage Input voltage Input current Input RF level Storage temperature Electrostatic discharge Electrostatic discharge Symbol Vcc VIN IIN Pimax TSTG VESD1 VESD2 Condition / Note Min 0 - 0.3 -1 no damage human body model, 1) human body model, 2) -40 -1.0 TBD Max 7.0 Vcc+0.3 1 10 +125 +1.0 TBD Unit V V mA dBm C kV kV
1) pins IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD 2) all pins, exept IN_DTA, ASK/FSK, RE/SCLK; TE/SDTA, FS0/SDEN, FS1/LD Normal Operating Conditions Parameter Supply voltage Operating temperature Carrier frequency VCO frequency RO frequency Frequency deviation FSK data rate FM bandwidth ASK data rate DC Characteristics Symbol Vcc Ta fc fVCO fRO f RFSK fm RASK Condition
Min 2.5 -40 300 300 3 5
all parameters under normal operating conditions, unless otherwise stated; typical values at Ta = 23 C and Vcc = 3 V Parameter Standby current Idle current Symbol ISBY IIDLE Condition TE/SDTA=0, RE/SCLK=0 TE/SDTA=1, RE/SCLK=1 @ fi = 868.3 MHz TE/SDTA=0, RE/SCLK=1 VGAIN_LNA > 1.4 V @ fi = 868.3 MHz TE/SDTA=0, RE/SCLK=1 VGAIN_LNA < 0.8 V @ fi = 868.3 MHz TE/SDTA=1, RE/SCLK=0 ASK/FSK=1 @ fi = 868.3 MHz, @ Po = 0 dBm Min Typ 50 2.5 Max 100 3.2 Unit nA mA
P
L E R
IRX_low IRX_high
at FM or FSK NRZ NRZ
IN IM
Y R A
Max Unit 5.5 +85 930 930 12 120 60 20 60 V C MHz MHz MHz kHz kbit/s kHz kbit/s
Total supply current in receive mode at low gain
6.0
8.0
mA
Total supply current in receive mode at high gain
7.0
9.0
mA
Total supply current in transmit mode at 0 dBm power
ITX_0
9.0
11.5
mA
3901007121 Rev. 001
Page 16 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
AC System Characteristics of the Receiver Part all parameters under normal operating conditions, unless otherwise stated; all parameters based on test circuits for FSK (Fig. 4 to 5), FM and ASK (Fig. 6 to 7), respectively; RF at 868.3 MHz Parameter Input sensitivity - FSK Symbol Pmin_FSK Condition BIF = 150kHz f = 50 kHz (FSK/FM) -3 BER 310 BIF = 150kHz -3 BER 310 -3 BER 310 VGAIN_LNA > 1.4 V -3 BER 310 VGAIN_LNA < 0.8 V -3 BER 310 VGAIN_LNA > 1.4 V -3 BER 310 VGAIN_LNA < 0.8 V fblock > 2MHz, note 1 TE/SDTA=0, RE/SCLK=1 valid data at output depends on ASK detector time constant and start-up mode, valid data at output Min Typ -103 Max Unit dBm
Input sensitivity - ASK Maximum input signal - FSK/FM at low gain Maximum input signal - FSK/FM at high gain Maximum input signal - ASK at low gain Maximum input signal - ASK at high gain Image rejection Blocking immunity Start-up time - FSK/FM
Pmin_ASK Pmax_FSK_1 Pmax_FSK_0 Pmax_ASK_1 Pmax_ASK_0 Pimag Pblock TFSK TASK
-105 10 -10 -20 0
dBm dBm dBm dBm
Start-up time - ASK
Spurious emission
Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal
AC System Characteristics of the Transmitter Part all parameters under normal operating conditions, unless otherwise stated; typical values at Ta = 23 C and Vcc = 3 V; TE/SDTA=1, RE/SCLK=0, ASK/FSK=1, RPS15 k, fc = 868.3 MHz, test circuit shown in Fig. 4 to 7 Parameter Output power FSK deviation Data rate FSK FM deviation Modulation frequency FM Data rate ASK PLL spurs emission Harmonic emission VCO gain Charge pump current Start-up time Symbol Po fFSK RFSK fFM fmod RASK Pspur Pharm KVCO ICP TTX Condition CW mode depends on Cx1, Cx2 and crystal parameter adjustable with varactor and VFM Min 4 5 Typ 6 50 60 6 5 60 at all fc and nominal Po at all fc and power steps 35 260 -36 -36 Max 8 100 Unit dBm kHz kbit/s kHz kHz kbit/s dBm dBm MHz/V A ms
P
L E R
Pspur
IN IM
Y R A
dBm dB dB ms TBD TBD 1 TFSK + 200K * C6 -70 ms dBm
from "standby" to "transmit" mode
1
3901007121 Rev. 001
Page 17 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Output Power Selection typical values at Ta = 23 C and Vcc = 3 V: TE/SDTA = 1, RE/SCLK = 0, ASK/FSK = 1, fc = 868.3 MHz, CW mode RPS / k ICC / mA PO / dBm Pharm / dBm 15 k TBD 6 -36 6.8 k 9.0 0 -36 3.3 k TBD -6 -36 1.0 k TBD -15 -36
Serial Control Interface Parameter Data to clock set up time Data to clock hold time Clock pulse width high Clock pulse width low Symbol fCS tCH tCWH tCWL tES Condition Min 150 50 100 100 100
Clock to load enable set up time
Crystal Parameters Parameter Crystal frequency
Load capacitance
P
IN IM L E R
Symbol fcrystal Cload C0 Rm Condition Min 3 fundamental mode, AT 10
Y R A
Max Unit ns ns ns ns Max 12 15 7 70 Unit MHz pF pF
Static capacitance Motional resistance
3901007121 Rev. 001
Page 18 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Application Circuit Examples
Programmable Channel FSK Application Circuit
VCC
CB3
RB VD1
CF1
CF2
RF input RF output
CB2
L0
RF RF1 CB6
FS0/SDEN
Lock detect
RPS C0 LTX0
TNK_LO VEE
Antenna matching network
CB1
CTX0
OUT_PA IN_LNA
P
IN IM L E R
CRX0 L1
VEE OUT_LNA ASK/FSK
RE/SCLK
VCC
Y R A
SDEN SDTA SCLK CB7
VCC
LF
C1
FS1/LD
VCC
VEE
GAIN_LNA IN_MIX VEE
IN_DTA
C2
CX2
FSK input
CX1
FSK_SW
OUT_DEM
IN_DEM
IN_IFA
OUT_MIX
OUT_DTA
RO
RSSI
XTAL
VEE
INT2
INT1
VCC
CB5 CERFIL CERRES CB4
C3
RSSI
C4 RP CP0 C5 CB0
FSK output
VCC
VCC
Figure 4:
Test circuit for programmable channel FSK operation
3901007121 Rev. 001
Page 19 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Fixed-Frequency FSK Application Circuit
VCC
CB3
RB VD1
CF1
CF2
RF input RF output
CB2
L0
RF RF1 CB6
RPS C0 LTX0
TNK_LO VEE
Antenna matching network
CB1
CTX0
OUT_PA IN_LNA
P
IN IM L E R
CRX0 L1
VEE OUT_LNA
RE/SCLK
VCC
Y R A
CB7
LF
FS1/LD
VCC
VEE
FS0/SDEN
TX enable RX enable
VCC
ASK/FSK IN_DTA
C1
GAIN_LNA IN_MIX VEE
C2
CX2
FSK input
CX1
FSK_SW RO
OUT_DEM
IN_DEM
IN_IFA
OUT_MIX
OUT_DTA
RSSI
XTAL
VEE
INT2
INT1
VCC
CB5 CERFIL CERRES CB4
C3
RSSI
C4 RP CP0 C5 CB0
FSK output
VCC
VCC
Figure 5:
Test circuit for fixed-frequency FSK operation at 868 MHz
3901007121 Rev. 001
Page 20 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
FSK test circuit component list to Fig. 4 and Fig. 5 Part
C0 C1 C2 C3 C4 C5 CB0 CB1 to CB4 CB5 CB6 CB7 CF1 CF2 CX1 CX2 CP0 CRX0 CTX0 RB RP RF RF1 RPS L0 L1 LTX0 VD1 XTAL CERFIL
Size
0805 0603 0603 0805 0805 0805 0805 0805 0603 0603 0603 0603 0805 0805 0805 0805 0805 0603 0603 0805 0805 0805 0805 0805
Value @ 868.3 MHz
8.2 pF NIP 1 pF 10 nF 100 pF 330 pF 100 nF 330 pF 330 pF 10 nF 330 pF 2.2 nF 100 pF 15 pF 33 pF 10 - 12 pF 100 pF 10 pF
Tolerance
5% 5% 5% 10% 10% 10% 10% 10% 10% 10% 10% 5% 5% 5% 5% VCO tank capacitor
Description
LNA output tank capacitor MIX input matching capacitor data slicer capacitor demodulator output low-pass capacitor, depending on data rate RSSI output low pass capacitor blocking capacitor blocking capacitor blocking capacitor blocking capacitor blocking capacitor loop filter capacitor loop filter capacitor RO capacitor
P
0805 0603 0805
L E R
3.9 K 82 k 9.1 k NIP 2.2 nH 10 nH 2.2 nH // 2.7 pF BBY-03W 7.1505 MHz SFE10.7MFP @ BIF2 = 40 kHz SFECV10.7MJS-A @ BIF2 = 150 kHz CDACV10.7MG18-A
10
10% 5% 5%
IN IM
5% 5% RX coupling capacitor 5% TX coupling capacitor loop filter resistor 5% loop filter resistor 5% 5% 5% 5%
RO capacitor for FSK (f = 20 kHz) CERRES parallel capacitor
Y R A
blocking resistor for VCC CERFIL parallel resistor
power-select resistor, only required at fixed-frequency operation VCO tank inductor LNA output tank inductor TX impedance matching inductor varactor diode from Infineon fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70 ceramic filter from Murata ceramic filter from Murata ceramic demodulator tank from Murata
SOD-323 HC49-SMD Leaded type SMD type SMD type
30ppm calibr. 30ppm temp. TBD 40 kHz
CERRES
Notes: * NIP - not in place, may be used optionally * Antenna matching network according to Evaluation Board Description EVB7120
3901007121 Rev. 001
Page 21 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Programmable Channel ASK Application Circuit
VCC
CB3
RB VD1
CF1
CF2
RF input RF output
CB2
L0
RF RF1 CB6
FS0/SDEN
Lock detect
RPS C0 LTX0
TNK_LO VEE
Antenna matching network
CB1
CTX0
OUT_PA IN_LNA
P
IN IM L E R
CRX0 L1
VEE OUT_LNA ASK/FSK
RE/SCLK
VCC
Y R A
SDEN SDTA SCLK CB7
VCC
LF
C1
FS1/LD
VCC
VEE
GAIN_LNA IN_MIX VEE
IN_DTA
C2
CX2
ASK input
CX1
FSK_SW
OUT_DEM
IN_DEM
IN_IFA
OUT_MIX
OUT_DTA
RO
RSSI
XTAL
VEE
INT2
INT1
VCC
CB5 CERFIL CB4 CERRES
C3
RSSI
C5 CB0
ASK output
VCC
VCC
Figure 6:
Test circuit for programmable channel ASK operation
3901007121 Rev. 001
Page 22 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Fixed-Frequency ASK Application Circuit
VCC
CB3
RB VD1
CF1
CF2
RF input RF output
CB2
L0
RF RF1 CB6
RPS C0 LTX0
TNK_LO VEE
Antenna matching network
CB1
CTX0
OUT_PA IN_LNA
P
IN IM L E R
CRX0 L1
VEE OUT_LNA
RE/SCLK
VCC
Y R A
CB7
LF
FS1/LD
VCC
VEE
FS0/SDEN
TX enable RX enable
VCC
ASK/FSK IN_DTA
C1
GAIN_LNA IN_MIX VEE
C2
CX2
ASK input
CX1
FSK_SW RO
OUT_DEM
IN_DEM
IN_IFA
OUT_MIX
OUT_DTA
RSSI
XTAL
VEE
INT2
INT1
VCC
CB5 CERFIL CB4 CERRES
C3
RSSI
C5 CB0
ASK output
VCC
VCC
Figure 7:
Test circuit for fixed-frequency ASK operation at 868 MHz
3901007121 Rev. 001
Page 23 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
ASK test circuit component list to Fig. 6 and Fig. 7 Part
C0 C1 C2 C3 C5 CB0 CB1 to CB3 CB5 CB6 CB7 CF1 CF2 CX1 CRX0 CTX0 RB RF RPS L0 L1 LTX0 XTAL CERFIL
Size
0805 0603 0603 0805 0805 0805 0805 0603 0603 0603 0603 0805 0805 0805 0603 0603 0805 0805 0805 0805 0603 0805
Value @ 868.3 MHz
8.2 pF NIP 1 pF 10 nF 330 pF 100 nF 330 pF 330 pF 10 nF 330 pF 2.2 nF 100 pF 15 pF 100 pF 10 pF 10 9.1 k NIP
Tolerance
5% 5% 5% 10% 10% 10% 10% 10% 10% 10% 5% 5% 5% 5% 5% 10% 5% 5% VCO tank capacitor
Description
LNA output tank capacitor MIX input matching capacitor data slicer capacitor RSSI output low pass capacitor blocking capacitor blocking capacitor blocking capacitor blocking capacitor blocking capacitor loop filter capacitor loop filter capacitor RO capacitor RX coupling capacitor TX coupling capacitor loop filter resistor
HC49-SMD
Notes: * NIP - not in place, may be used optionally * Antenna matching network according to Evaluation Board Description EVB7120
P
Leaded type SMD type
L E R
2.2 nH 10 nH 82 nH 7.1505 MHz SFE10.7MFP @ BIF2 = 40 kHz SFECV10.7MJS-A @ BIF2 = 150 kHz
30ppm calibr. 30ppm temp. TBD 40 kHz
IN IM
5% 5% 5%
blocking resistor for VCC
power-select resistor, only required at fixed-frequency operation VCO tank inductor LNA output tank inductor TX impedance matching inductor
Y R A
fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70
ceramic filter from Murata ceramic filter from Murata
3901007121 Rev. 001
Page 24 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Programmable Channel FSK Application Circuit with AFC
VCC
CB3
RB VD1
CF1
CF2
RF input RF output
CB2
L0
RF RF1 CB6
FS0/SDEN
Lock detect
RPS C0 LTX0
TNK_LO VEE
Antenna matching network
CB1
CTX0
OUT_PA IN_LNA
P
IN IM L E R
CRX0 L1
VEE VCC OUT_LNA ASK/FSK
RE/SCLK
Y R A
SDEN SDTA SCLK CB7
VCC
LF
C1
FS1/LD
VCC
VEE
GAIN_LNA IN_MIX VEE
IN_DTA
C2
CX2
FSK input
CX1
FSK_SW
OUT_DEM
IN_DEM
IN_IFA
OUT_MIX
OUT_DTA
RO
RSSI
XTAL
VEE
INT2
INT1
VCC
CB5 CERFIL CERRES CP1 CB4
C3
RSSI
R2 C4 C5 CB0 VD
FSK output
VCC
VCC
Figure 8:
Test circuit for programmable channel FSK operation with AFC
Circuit Features ! ! ! ! Automatic Frequency Control (AFC) Increases input frequency acceptance range up to RFnom 50 kHz Compensation of calibration tolerances of ceramic resonator Compensation of temperature tolerances of ceramic resonator
3901007121 Rev. 001
Page 25 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Fixed-Frequency FSK Application Circuit with AFC
VCC
CB3
RB VD1
CF1
CF2
RF input RF output
CB2
L0
RF RF1 CB6
RPS C0 LTX0
TNK_LO VEE
Antenna matching network
CB1
CTX0
OUT_PA IN_LNA
CRX0 L1
VEE OUT_LNA
P
! ! ! !
L E R
C1 C2
IN_MIX VEE IN_IFA OUT_MIX
GAIN_LNA
IN IM
OUT_DEM IN_DEM RSSI INT2 INT1 VCC
RE/SCLK
VCC
Y R A
CB7
LF
FS1/LD
VCC
VEE
FS0/SDEN
TX enable RX enable
VCC
ASK/FSK IN_DTA
CX2
FSK input
CX1
FSK_SW RO
OUT_DTA
XTAL
VEE
CB5 CERFIL CERRES CP1 CB4
C3
RSSI
R2 C4 C5 CB0 VD
FSK output
VCC
VCC
Figure 9:
Test circuit for fixed-frequency FSK operation at 868 MHz with AFC
Circuit Features Automatic Frequency Control (AFC) Increases input frequency acceptance range up to RFnom 50 kHz Compensation of calibration tolerances of ceramic resonator Compensation of temperature tolerances of ceramic resonator
3901007121 Rev. 001
Page 26 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Package Dimensions
D D1
24 17
25
16
b e
E
E1
32 9
1
8
A
A2
A1
P
All Dimension in mm, coplanarity < 0.1mm E1, D1 7.00 max min 0.276 max 0.630 0.006 0.057 1.60 0.15 0.002 1.45 0.053 0.031 0.018 0.030 A A1 0.05 A2 1.35 0.8 0.45 0.012 0.75 0.018 0.354 7 e b 0.30 L 0.45 9.00 7 0 E, D 0 min
L E R
Fig. 7: LQFP32 (Low Quad Flat Package)
IN IM
L
Y R A
All Dimension in inch, coplanarity < 0.004"
3901007121 Rev. 001
Page 27 of 28
Data Sheet Jan. 2002
TH7121
300 to 930MHz FSK/FM/ASK Transceiver
Your Notes
Important Notice
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis' rendering of technical or other services. (c) 2000 Melexis GmbH. All rights reserved.
P
L E R
IN IM
Y R A
For the latest version of this document. Go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe and Japan:
Phone: +32 1361 1631
All other locations:
Phone: +1 603 223 2362
QS9000, VDA6.1 and ISO14001 Certified 3901007121 Rev. 001 Page 28 of 28 Data Sheet Jan. 2002

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